View 74ABT544D_471988.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
* ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per Machine Model
74ABT544
FEATURES
* Combines 74ABT245 and 74ABT373 type
functions in one device
FUNCTIONAL DESCRIPTION
The 'ABT544 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (EAB) input and the A-to-B Latch Enable (LEAB) input are Low the A-to-B path is transparent. A subsequent Low-to-High transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both Low, the 3-State B output buffers are active and invert the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.
* 8-bit octal transceiver with D-type latch * Back-to-back registers for storage * Separate controls for data flow in each
direction
DESCRIPTION
The 74ABT544 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT544 Octal Registered Transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA.
* Output capability: +64mA/-32mA * Live insertion/extraction permitted * Power-up 3-State * Power-up reset * Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
ORDERING INFORMATION
PACKAGES 24-pin plastic DIP 24-pin plastic SOL 24-pin plastic SSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C ORDER CODE 74ABT544N 74ABT544D 74ABT544DB DRAWING NUMBER 0410D 0173D 1641A
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
2 23 1EN3 (AB) G1 1C5 2EN4 (BA) G2 2C6 22 5D 4 21 20 19 18 17 16 15
LEBA OEBA
1 2
24 VCC 23 EBA 22 B0 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 15 B7 11 23 A0 A1 A2 A3 A4 A5 A6 A7 EAB EBA LEAB LEBA B0 B1 B2 B3 B4 B5 B6 B7 OEAB OEBA 13 2 3 4 5 6 7 8 9 10
1 13 11 14
A0 3 A1 4 A2 A3 5 6
3 4
3 5D
A4 7 A5 8 A6 9
14 1
5 6 7 8
A7 10 EAB 11 GND 12
14 LEAB 13 OEAB
22 21 20 19 18 17 16 15 9 10
June 1, 1993
1
853-1610 09907
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
PIN DESCRIPTION
PIN NUMBER 14, 1 11, 23 13, 2 3, 4, 5, 6, 7, 8, 9, 10 22, 21, 20, 19, 18, 17, 16, 15 12 24 SYMBOL LEAB / LEBA EAB / EBA OEAB / OEBA A0 - A7 B0 - B7 GND VCC FUNCTION A to B / B to A Latch Enable input (active-Low) A to B / B to A Enable input (active-Low) A to B / B to A Output Enable input (active-Low) Port A, 3-State outputs Port B, 3-State outputs Ground (0V) Positive supply voltage
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC = 5.5V TYPICAL 3.9 4 7 110 UNIT ns pF pF A
June 1, 1993
2
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
LOGIC DIAGRAM
DETAIL A D LE Q 22 B0
A0
3 Q D LE
A1 A2 A3 A4 A5 A6 A7
4 5 6 7 8 9 10 DETAIL A X 7
21 20 19 18 17 16 15
B1 B2 B3 B4 B5 B6 B7
OEBA
2 13
OEAB
EBA
23 11
LEBA
1
EAB
14
LEAB
FUNCTION TABLE
INPUTS OEXX H X L L L L L L L H= h= L= l= X= = NC= Z= EXX X H L L L L LEXX X X L L L L An or Bn X X h l h l H L OUTPUTS An or Bn Z Z Z Z L H L H Disabled Disabled Disabled + Latch Latch + Display Transparent STATUS
L H X NC Hold High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition Don't care Low-to-High clock transition No change High impedance or "off" state
June 1, 1993
3
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 10 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V C UNIT
June 1, 1993
4
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II Low-level output voltage Power-up output low voltage3 Input leakage current IOFF IPU/PD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VI or VO 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V -50 2.5 3.0 2.0 Typ -0.9 3.2 3.7 2.3 0.42 0.13 0.01 5 5.0 5.0 5.0 -5.0 5.0 -65 110 20 110 0.3 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 -50 Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A A A A A A mA A mA A mA UNIT
Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output high leakage current Output current1
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition of 10msec. From VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100sec is permitted.
June 1, 1993
5
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation delay An to Bn, Bn to An Propagation delay LEBA to An, LEAB to Bn Output enable time OEBA to An, OEAB to Bn Output disable time OEBA to An, OEAB to Bn Output enable time EBA to An, EAB to Bn Output disable time EBA to An, EAB to Bn 2 1, 2 4 5 4 5 4 5 4 5 1.1 1.4 1.6 2.1 1.4 2.5 2.5 1.0 1.4 2.5 2.5 1.0 Tamb = +25oC VCC = +5.0V Typ 3.6 3.9 4.1 4.6 3.9 5.0 5.9 5.5 3.9 5.0 5.9 5.5 Max 5.1 5.4 5.6 6.1 5.4 6.5 7.4 7.0 5.4 6.5 7.4 7.0 Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 1.1 1.4 1.6 2.1 1.4 2.5 3.4 3.0 1.4 2.5 3.4 3.0 Max 6.1 6.4 6.6 7.1 6.4 7.5 8.4 8.0 6.4 7.5 8.4 8.0 ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = VCC = +5.0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(L) Setup time An to LEAB, Bn to LEBA Hold time An to LEAB, Bn to LEBA Setup time An to EAB, Bn to EBA Hold time An to EAB, Bn to EBA Latch enable pulse width, Low 3 3 3 3 3 3.0 3.0 0.5 0.5 3.0 3.0 0.5 0.5 3.5 +25oC Typ 1.5 0.6 -0.3 -1.3 1.5 0.6 -0.2 -1.3 1.8 Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 3.0 3.0 0.5 0.5 3.0 3.0 0.5 0.5 3.5 ns ns ns ns ns UNIT
June 1, 1993
6
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
VIN
VM tPHL
VM tPLH VM VM
VIN
VM tPLH
VM tPHL VM VM
VOUT
VOUT
Waveform 1. Propagation Delay For Inverting Output
An, Bn
VM
VM
ts(H)
LEAB, LEBA
VM
Waveform 3. Data Setup and Hold Times And Latch Enable Pulse Width OEAB, OEBA, EAB, EBA OEAB, OEBA, EAB, EBA
tPHZ VOH -0.3V 0V
VM tPZH
VM
An, Bn
VM
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
June 1, 1993
EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E
VM VM th(H) ts(L) th(L) tw(L) VM VM tPZL
EEE EEE EEE EEE
Waveform 2. Propagation Delay For Non-Inverting Output
VM tPLZ
An, Bn
VM VOL +0.3V 0V
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
7
Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T CL RL VOUT RL
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
AMP (V)
0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V)
Test Circuit for 3-State Outputs
POSITIVE PULSE 10%
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
June 1, 1993
8

▲Up To Search▲

Price & Availability of 74ABT544D

	To Download 74ABT544D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .